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CompuLab Ltd. IPC2 – Hardware Specification Page 26 of 83

3.5.1 Functional Blocks

Figure 3 – PCH Internal Clock Diagram

The PCH has one main PLL in which its output is divided down through Modulators and Dividers

to provide great flexibility in clock source selection, configuration, and better power management.

Table 15 describes the PLLs on the PCH and the clock domains that are driven from the PLLs.

Table 15 – PCH PLL

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 82 83

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