CompuLab Trim-Slice Instrukcja Użytkownika Pobierz pdf (Strona 13)

Interfaces and Connectors

Revised July 2011 Trim-Slice 13

3.7 SATA Controller

The Trim-Slice SATA functionality is implemented with the Genesys Logic GL830 USB-to-SATA

controller. The controller supports the following main features:

 Compliance with Universal Serial Bus specification rev. 2.0

 Compliance with USB Storage Class specification ver.1.0

 Compliance with Serial ATA specification rev. 2.6

 Compliance with Serial ATA II Electrical Specification 1.0

The SATA controller is interfaced with the Tegra2 USB-1 port through the USB selector. The SATA

output signals are routed to connector P18.

NOTE: SATA functionality is optional. Availability depends on Trim-Slice model

configuration.

3.8 Video Decoder

The Trim-Slice video input port is implemented with the on-board Texas Instruments TVP5151 video

decoder that converts NTCS / PAL / SECAM composite analog video into digital 8-bit ITU-R

BT.656 format. The analog video input is routed to audio jack P4. The digital BT.656 data is

transmitted into the Tegra2 digital video input port.

For additional details, please refer to the TVP5151 datasheet, available from http://focus.ti.com/.

NOTE: Video decoder functionality is optional. Availability depends on Trim-Slice model

configuration.

3.9 RS232 Transceiver

The Trim-Slice RS232 port is implemented with the MAX3243 transceiver.

The RS232 port supports the following features:

 16550 compatibility

 16-byte FIFO for receiver and 16-byte FIFO for transmitter

 Programmable baud rate of up to 250 Kbps

 Configurable data format

 RS-232 bus-pin ESD protection exceeds ±15 kV using the Human-Body Model

The RS232 port is derived from the UART-1 port of the Tegra2 SoC.

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CompuLab Trim-Slice Instrukcja Użytkownika Strona 13